In conventional stacked chip packaging systems and methods, a great deal of effort and cost is expended in connecting one layer to another and to an outside connection.
FIG. 1 illustrates a conventional approach to configuring die and packages with wire bond in both same size packages and different size packages. FIGS. 1A and 1C illustrate different size die (FIG. 1A) and packages (FIG. 1C), where the stacking is on a stair case shape. In each package, connections must be made on the outside of the die edges, or otherwise made through the die substrates. FIGS. 1B and 1D illustrate equal size die (FIG. 1B) and packages (FIG. 1D), where the stacking is on a rectangular configuration. Like the other package configurations illustrated in FIGS. 1A and 1C, in each package, connections must be made on the outside of the die edges, or otherwise made through the die substrates. In an assembly of the same size packages, a thick adhesive is used to clear the wire bond loop.
Referring to FIG. 2, a stacked chip package is illustrated having solder balls in between same sized stacked layers of the package. In processing such a package, wide variations in temperature greatly affect the ability to stack and connect the different layers. Also, the connections are difficult to make from layer to layer, and are done upon processing and assembly of the package.
Table 1 compares and contrasts the features and benefits of three exemplary ways of stacking, i.e., solder ball stacking of equal sized packages, wire bond stacking of equal size packages, and wire bond stacking of different size packages. The configurations are compared in terms of adhesive thickness, individual chip select, inventory management, package width, JEDEC ball out, and whether or not the die is exposed.
TABLE 1Reported package stackingSolder ball stackingWire bond stackingPackage sizeSameSameDifferentAdhesiveTHINTHICKTHIN(total packagethickness)Chip select requiredYESNONOin individual packageInventory issueYESNOYESPackage widthWIDENARROWNARROWJEDEC ball outNOYESYESExposed dieYESNONOThe comparison shows the need for a multi-level packaging strategy that optimizes the trade-off between package size, adhesive thickness, chip access, inventory management, package width, JEDEC ball out, and dies exposure. As will be seen, the invention optimizes these features in an elegant manner.